The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Dec. 21, 2012
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Gautam Chakrabarti, Santa Clara, CA (US);

Yuan Lin, Santa Clara, CA (US);

Jaydeep Marathe, Santa Clara, CA (US);

Okwan Kwon, West Lafayette, IN (US);

Amit Sabne, West Lafayette, IN (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01); G06F 12/02 (2006.01); G06F 9/45 (2006.01); G06F 9/52 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/38 (2013.01); G06F 8/40 (2013.01); G06F 9/5016 (2013.01); G06F 9/52 (2013.01); G06F 9/522 (2013.01); G06F 12/02 (2013.01);
Abstract

A system and method for executing sequential code in the context of a single-instruction, multiple-thread (SIMT) processor. In one embodiment, the system includes: (1) a pipeline control unit operable to create a group of counterpart threads of the sequential code, one of the counterpart threads being a master thread, remaining ones of the counterpart threads being slave threads and (2) lanes operable to: (2) execute certain instructions of the sequential code only in the master thread, corresponding instructions in the slave threads being predicated upon the certain instructions and (2) broadcast branch conditions in the master thread to the slave threads.


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