The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Mar. 14, 2014
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Blake A. Hechtman, Bellevue, WA (US);

Shuai Che, Bellevue, WA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/26 (2006.01); G06F 3/06 (2006.01); G06F 12/10 (2016.01); G06F 9/52 (2006.01); G06F 9/54 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 3/0637 (2013.01); G06F 9/52 (2013.01); G06F 9/54 (2013.01); G06F 12/1081 (2013.01); G06F 12/1491 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/657 (2013.01);
Abstract

Central processing units (CPUs) in computing systems manage graphics processing units (GPUs), network processors, security co-processors, and other data heavy devices as buffered peripherals using device drivers. Unfortunately, as a result of large and latency-sensitive data transfers between CPUs and these external devices, and memory partitioned into kernel-access and user-access spaces, these schemes to manage peripherals may introduce latency and memory use inefficiencies. Proposed are schemes to reduce latency and redundant memory copies using virtual to physical page remapping while maintaining user/kernel level access abstractions.


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