The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

May. 20, 2014
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventors:

Takashi Aoki, Kawasaki, JP;

Takahiro Korenari, Kawasaki, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 23/482 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41741 (2013.01); H01L 23/4824 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7809 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01); H01L 29/0638 (2013.01); H01L 29/1095 (2013.01); H01L 29/41766 (2013.01); H01L 29/42372 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/11 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/131 (2013.01); H01L 2924/13055 (2013.01);
Abstract

A semiconductor device including an active cell region formed over the surface of a silicon substrate and including a vertical MOSFET, a drain electrode formed over the surface of the silicon substrate and leading out the drain of the vertical MOSFET from the back surface of the silicon substrate, an external drain terminal formed over the drain electrode, and a source electrode formed over the active cell region so as to be opposed to the drain electrode at least along three sides at the periphery of the external drain terminal over the active cell region and connected to the source of the vertical MOSFET.


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