The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Oct. 29, 2014
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Yoshiaki Oikawa, Tochigi, JP;

Hotaka Maruyama, Tochigi, JP;

Hiromichi Godo, Isehara, JP;

Daisuke Kawae, Atsugi, JP;

Shunpei Yamazaki, Setagaya, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1214 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01); H01L 29/78693 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01);
Abstract

An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOis used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOand a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiO. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiO.


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