The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Jan. 01, 2015
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Xinpeng Wang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/28273 (2013.01); H01L 21/762 (2013.01); H01L 21/76205 (2013.01); H01L 27/11548 (2013.01); H01L 29/42324 (2013.01);
Abstract

A method is provided for fabricating a flash memory device. The method includes providing a semiconductor substrate; and forming a first polysilicon layer. The method also includes forming a hard mask layer; and forming a plurality of first openings exposing the first polysilicon layer in the hard mask layer and the first polysilicon layer. Further, the method includes forming a plurality of grooves by etching the semiconductor substrate along the first openings; and forming liner oxide layers by oxidizing the first polysilicon layer. Further, the method also includes forming shallow trench isolation structures by filling the first openings; and forming second openings by removing the hard mask layer and the non-oxidized first polysilicon layer. Further, the method also includes forming a tunnel oxide layer on a bottom of the second opening; and forming a floating gate on each of the tunnel oxide layers.


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