The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

May. 10, 2012
Applicants:

Yun-hyuck Ji, Gyeonggi-do, KR;

Kwan-woo DO, Gyeonggi-do, KR;

Beom-yong Kim, Gyeonggi-do, KR;

Seung-mi Lee, Gyeonggi-do, KR;

Woo-young Park, Gyeonggi-do, KR;

Inventors:

Yun-Hyuck Ji, Gyeonggi-do, KR;

Kwan-Woo Do, Gyeonggi-do, KR;

Beom-Yong Kim, Gyeonggi-do, KR;

Seung-Mi Lee, Gyeonggi-do, KR;

Woo-Young Park, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/108 (2006.01); H01L 21/20 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10808 (2013.01); H01L 21/2018 (2013.01); H01L 27/10873 (2013.01); H01L 27/10885 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.


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