The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Jul. 01, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Gregory Costrini, Hopewell Junction, NY (US);

Ravikumar Ramachandran, Pleasantville, NY (US);

Reinaldo A. Vega, Wappingers Falls, NY (US);

Richard S. Wise, Newburgh, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/3081 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 29/0653 (2013.01); H01L 29/517 (2013.01); H01L 29/6681 (2013.01);
Abstract

Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors.


Find Patent Forward Citations

Loading…