The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Feb. 27, 2015
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Rolf Weis, Dresden, DE;

Franz Hirler, Isen, DE;

Martin Feldtkeller, Munich, DE;

Gerald Deboy, Klagenfurt, AT;

Matthias Stecher, Munich, DE;

Armin Willmeroth, Augsburg, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); H03K 3/00 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 27/07 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 27/0623 (2013.01); H01L 27/0629 (2013.01); H01L 27/0727 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 29/7824 (2013.01); H01L 29/7835 (2013.01); H01L 29/7838 (2013.01); H01L 29/0653 (2013.01); H01L 29/0692 (2013.01);
Abstract

Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.


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