The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2016
Filed:
Jul. 11, 2014
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Yi-Koan Hong, Suwon-si, KR;
Byung-Lyul Park, Seoul, KR;
Ji-Soon Park, Suwon-si, KR;
Si-Young Choi, Seongnam-si, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 23/528 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80894 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12044 (2013.01);
Abstract
Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.