The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Feb. 19, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Toshiaki Kirihata, Poughkeepsie, NY (US);

Edward P. Maciejewski, Wappingers Falls, NY (US);

Subramanian S. Iyer, Mount Kisco, NY (US);

Chengwen Pei, Danbury, CT (US);

Deepal U. Wehella-Gamage, Newburgh, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/525 (2006.01); H01L 21/768 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5256 (2013.01); H01L 21/76886 (2013.01); H01L 21/84 (2013.01); H01L 23/5252 (2013.01); H01L 27/1203 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged.


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