The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Nov. 30, 2009
Applicants:

Michael Priel, Hertzelia, IL;

Leonid Fleshel, Hertzelia, IL;

Anton Rozen, Gedera, IL;

Inventors:

Michael Priel, Hertzelia, IL;

Leonid Fleshel, Hertzelia, IL;

Anton Rozen, Gedera, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/58 (2006.01); H01L 23/495 (2006.01); G11C 29/50 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 22/22 (2013.01); H01L 23/5286 (2013.01); H01L 23/585 (2013.01); G11C 2029/5002 (2013.01); H01L 22/14 (2013.01); H01L 23/49589 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.


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