The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

May. 23, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jee-Eun Jung, Yongin-si, KR;

Kyoung-Yun Baek, Suwon-si, KR;

Jeong-Hoon Lee, Yongin-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/33 (2006.01); H01L 21/033 (2006.01); G03F 1/00 (2012.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0338 (2013.01); G03F 1/00 (2013.01); H01L 21/0274 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 22/12 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes generating a mask layout of patterns in which the distance between adjacent ones of the patterns is equal to or less than a resolution of a lithography process, the patterns are apportioned among a plurality of masks such that in each of the masks the space between adjacent ones of the patterns is greater than the resolution, and a dual pattern is added to one of the masks. A semiconductor pattern is formed on a substrate using the mask(s) and the mask to which the dual pattern has been added. Patterns having a pitch equal to or less than the resolution may be formed on the semiconductor device.


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