The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Mar. 13, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Assaf Shacham, Zichron Yaakov, IL;

Amit Gil, Zichron Yaakov, IL;

Erez Tsidon, Moreshet, IL;

Yanru Li, San Diego, CA (US);

Azzedine Touzni, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/52 (2006.01); G06F 9/54 (2006.01); G11C 7/10 (2006.01); G06F 1/32 (2006.01); G06F 9/46 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1075 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 9/462 (2013.01); G06F 9/463 (2013.01); G06F 9/52 (2013.01); G06F 9/544 (2013.01); G06F 11/0757 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1285 (2013.01);
Abstract

Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.


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