The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Sep. 09, 2015
Applicant:

Chaologix, Inc., Gainesville, FL (US);

Inventors:

Daniel F. Yannette, Indialantic, FL (US);

Brent Arnold Myers, Palm Bay, FL (US);

Assignee:

CHAOLOGIX, INC., Gainesville, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); G06F 21/81 (2013.01); H03K 19/003 (2006.01); H03K 19/0948 (2006.01); G06F 21/55 (2013.01);
U.S. Cl.
CPC ...
G06F 21/81 (2013.01); G06F 21/558 (2013.01); H03K 19/00315 (2013.01); H03K 19/0948 (2013.01); G06F 2221/034 (2013.01);
Abstract

Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.


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