The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Apr. 10, 2014
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Jong Kim, Tempe, AZ (US);

James Spehar, Chandler, AZ (US);

Xu Zhang, Chandler, AZ (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 23/64 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5036 (2013.01); G06F 17/5077 (2013.01); G06F 2217/40 (2013.01); H01L 23/64 (2013.01); H01L 25/0655 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Various example embodiments are directed to methods and apparatuses for implementing a circuit design within an integrated circuit (IC) package. A respective capacitance is determined for each die contact of a circuit design. A respective target inductance range is selected for each of the plurality of die contacts based on the determined capacitance. A segmentation of the circuit design is determined as a function of the target inductance ranges. The segmentation defines an implementation of the circuit design on a plurality of IC dies. The IC dies are placed at respective locations on the substrate, based on the resulting inductances of connections (e.g., conductive traces) between the die contacts and terminals of the IC package.


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