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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9430432 B1

PDFFull Text
Date of Patent:
Aug. 30, 2016

Filed:

Apr. 20, 2012

Optimized multi-root input output virtualization aware switch

Applicants:

Balaji Kanigicherla, Andhra Pradesh, IN;

Dhanumjai Pasumarthy, Andhra Pradesh, IN;

Shabbir Haider, Andhra Pradesh, IN;

Naga Murali Medeme, Andhra Pradesh, IN;

Paulraj Kanakaraj, Andhra Pradesh, IN;

Tapan Vaidya, Andhra Pradesh, IN;

Inventors:

Balaji Kanigicherla, Andhra Pradesh, IN;

Dhanumjai Pasumarthy, Andhra Pradesh, IN;

Shabbir Haider, Andhra Pradesh, IN;

Naga Murali Medeme, Andhra Pradesh, IN;

Paulraj Kanakaraj, Andhra Pradesh, IN;

Tapan Vaidya, Andhra Pradesh, IN;

Assignee:

Ineda Systems PVT. LTD., , IN;

Attorney:

Workman Nydegger

Primary Examiner:

Henry Tsai

Assistant Examiner:

Christopher Bartels

Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 5/00 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/40 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0058 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

In one implementation, an optimized multi-root input-output virtualization (MRIOV) aware switch configured to route data between multiple root complexes and I/O devices is described. The MRIOV aware switch may include two or more upstream ports and one or more downstream ports. Each of an upstream port and a downstream port may include a media access controller (MAC) configured to negotiate link width and link speed for exchange of data packets between the multiple root complexes and the I/O devices. Each of an upstream port and a downstream port may further include a clocking module configured to dynamically configure a clock rate of processing data packets based one or more negotiated link width and negotiated link speed, and a data link layer (DLL) coupled to the MAC configured to operate at the clock rate, wherein the clock rate is indicative of processing speed.

Find Patent Forward Citations

Quick Actions:

Kanigicherla, Balaji. (2016). Optimized multi-root input output virtualization aware switch (U.S. Patent No. 9430432). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9430432

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