The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2016
Filed:
May. 23, 2014
Coherent Logix, Incorporated, Austin, TX (US);
Michael B. Doerr, Dripping Springs, TX (US);
Carl S. Dobbs, Austin, TX (US);
Michael B. Solka, Austin, TX (US);
Michael R. Trocino, Austin, TX (US);
Kenneth R. Faulkner, Austin, TX (US);
Keith M. Bindloss, Irvine, CA (US);
Sumeer Arya, Austin, TX (US);
John Mark Beardslee, Menlo Park, CA (US);
David A. Gibson, Austin, TX (US);
Coherent Logix, Incorporated, Austin, TX (US);
Abstract
Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.