Efficient branch predictor history recovery in pipelined computer architectures employing branch prediction and branch delay slots of variable size

Abstract

A pipelined processor employs branch prediction based on branch source instructions situated in a last one of a variable number of branch delay slots associated with a branch instruction. As each memory unit of data (UoD) progresses through the processing stages from one cycle to a next, a set of N branch prediction histories is built that is associated with the UoD, N being the number of cycles the branch predictor requires to produce an output. A history of evaluated branch outcomes of branch instructions that reached the branch evaluation stage is also maintained. Recovery from misprediction includes using the history of evaluated branch outcomes and the set of branch prediction histories associated with the UoD (readily available to a last stage of the pipeline) as a source of recovery histories for inputting to a branch predictor when N next memory units of data are loaded into the pipeline.