The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2016
Filed:
May. 28, 2015
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventor:
Jeong Tae Hwang, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, Gyeonggi-do, unknown;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); G01R 31/28 (2006.01); H03K 19/0185 (2006.01); H03K 3/356 (2006.01); H03K 17/10 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2856 (2013.01); G01R 31/2874 (2013.01); H03K 3/356104 (2013.01); H03K 17/102 (2013.01); H03K 17/6872 (2013.01); H03K 19/0005 (2013.01); H03K 19/018521 (2013.01);
Abstract
A semiconductor integrated circuit device having a function for detecting degradation of a semiconductor device and a method of driving the same are disclosed. The semiconductor integrated circuit device includes an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor, a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor, and a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor.