The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

May. 22, 2015
Applicant:

The United States of America As Represented BY the Secretary of the Navy, Washington, DC (US);

Inventors:

Adam Duncan, Bloomington, CA (US);

Matthew Gadlage, Bloomington, CA (US);

Austin Roach, Bloomfield, IN (US);

Matthew Kay, Jasper, IN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/177 (2006.01); G06F 12/14 (2006.01); G06F 12/16 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17768 (2013.01); G06F 12/14 (2013.01); G06F 12/1408 (2013.01); G06F 12/1433 (2013.01); G06F 12/1458 (2013.01); G06F 12/16 (2013.01);
Abstract

Methods and apparatuses for implementing a Physically Unclonable Function (PUF) and random number generator capabilities comprising providing a device under test comprising a plurality of bits comprising integrated circuits each including a capacitor; placing the bits in a first state with charge on selected bit capacitors; stopping bit refresh for a first predetermined time; re-enabling refresh for a second predetermined time to read and refresh charge on all bits; reading all bits and recording addresses of bits that have experienced bit flip from a first state to a second state comprising from '1' to '0' state; performing selecting a plurality of said recorded addresses to generate a PUF or cryptographic key; and performing an operation comprising a test or verification operation with said generated information PUF or key. Various hardware elements are also provided as well as machine readable instructions for implementing and controlling aspects of the invention.


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