The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Mar. 06, 2015
Applicant:

University of Hawaii, Honolulu, HI (US);

Inventors:

William Ditto, Kaneohe, HI (US);

Behnam Kia, Honolulu, HI (US);

Assignee:

University of Hawaii, Honolulu, HI (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03K 19/177 (2006.01); H03M 1/34 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17728 (2013.01); H03K 19/17744 (2013.01); H03M 1/34 (2013.01);
Abstract

The present invention provides apparatuses and methods for chaos computing. For example, a chaos-based logic block comprises an encoding circuit block, at least one chaotic circuit block, a bias voltage generating circuit block, and a threshold circuit block. The encoding circuit block converts a plurality of digital inputs to an analog output. The plurality of digital inputs may comprise at least one data input and at least one control input. At least one chaotic circuit block is configured to iterate converting an input signal to an output signal by feeding the output signal to at least one chaotic circuit as the input signal at each iteration. The bias voltage generating circuit block converts a plurality of binary control inputs to a bias voltage. The threshold circuit block compares the output signal with a predetermined threshold, thereby generating a digital signal.


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