The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Jan. 06, 2012
Applicants:

Roy G. Gordon, Cambridge, MA (US);

Damon B. Farmer, White Planes, NY (US);

Inventors:

Roy G. Gordon, Cambridge, MA (US);

Damon B. Farmer, White Planes, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 16/00 (2006.01); H01B 1/00 (2006.01); H01L 51/00 (2006.01); B82Y 10/00 (2011.01); B82Y 30/00 (2011.01); B82Y 40/00 (2011.01); C01B 31/02 (2006.01); C01F 7/30 (2006.01); H01L 51/05 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0049 (2013.01); B82Y 10/00 (2013.01); B82Y 30/00 (2013.01); B82Y 40/00 (2013.01); C01B 31/0273 (2013.01); C01F 7/304 (2013.01); C01B 2202/02 (2013.01); C01P 2004/13 (2013.01); H01L 51/057 (2013.01); H01L 51/0595 (2013.01); Y10S 977/734 (2013.01); Y10S 977/755 (2013.01); Y10S 977/842 (2013.01); Y10S 977/847 (2013.01); Y10S 977/89 (2013.01); Y10T 428/2918 (2015.01);
Abstract

There are provided methods for functionalizing a planar surface of a microelectronic structure, by exposing the surface to at least one vapor including at least one functionalization species, such as NOor CHONO, that non-covalently bonds to the surface while providing a functionalization layer of chemically functional groups, to produce a functionalized surface. The functionalized surface is exposed to at least one vapor stabilization species that reacts with the functionalization layer to form a stabilization layer that stabilizes the functionalization layer against desorption from the planar microelectronic surface while providing chemically functional groups. The stabilized surface is exposed to at least one material layer precursor species that deposits a material layer on the stabilized planar microelectronic surface. The stabilized planar microelectronic surface can be annealed at a peak annealing temperature that is less than about 700° C.


Find Patent Forward Citations

Loading…