The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Dec. 01, 2010
Applicant:

Andrew Norman, Evergreen, CO (US);

Inventor:

Andrew Norman, Evergreen, CO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0264 (2006.01); H01L 29/04 (2006.01); H01L 21/02 (2006.01); H01L 31/036 (2006.01); H01L 31/076 (2012.01); H01L 31/18 (2006.01); H01L 33/00 (2010.01); H01L 31/0725 (2012.01); H01L 33/26 (2010.01); H01L 31/056 (2014.01); H01L 33/12 (2010.01);
U.S. Cl.
CPC ...
H01L 29/04 (2013.01); H01L 21/0242 (2013.01); H01L 21/02365 (2013.01); H01L 21/02381 (2013.01); H01L 21/02395 (2013.01); H01L 21/02439 (2013.01); H01L 21/02491 (2013.01); H01L 21/02502 (2013.01); H01L 21/02521 (2013.01); H01L 31/036 (2013.01); H01L 31/056 (2014.12); H01L 31/076 (2013.01); H01L 31/0725 (2013.01); H01L 31/1852 (2013.01); H01L 33/007 (2013.01); H01L 33/26 (2013.01); H01L 33/12 (2013.01); Y02E 10/52 (2013.01); Y02E 10/544 (2013.01); Y02E 10/548 (2013.01);
Abstract

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method. As a result, the semiconductor devices provided herein possess enhanced performance characteristics due to a relatively low density of crystal defects.


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