The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Jun. 22, 2012
Applicants:

Richard Price, Sedgefield, GB;

Scott White, Sedgefield, GB;

Inventors:

Richard Price, Sedgefield, GB;

Scott White, Sedgefield, GB;

Assignee:

Pragmatic Printing Ltd, Sedgefield, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/12 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/768 (2006.01); H01L 27/088 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/0272 (2013.01); H01L 21/76817 (2013.01); H01L 27/1288 (2013.01); H01L 27/1292 (2013.01); H01L 29/66757 (2013.01); H01L 29/7869 (2013.01);
Abstract

A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.


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