The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Feb. 20, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventor:

Minghao Shen, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/14 (2006.01); H01L 23/15 (2006.01); H01L 21/48 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/486 (2013.01); H01L 23/147 (2013.01); H01L 23/15 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 25/065 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01);
Abstract

An interposer is provided. The interposer includes a silicon substrate layer, a glass substrate layer, and at least one through interposer via. The silicon substrate layer is formed on top of the glass substrate layer. The interposer may also be known as a hybrid interposer because it includes two different types of substrate layers forming one interposer. The through interposer via is formed to go through the silicon substrate layer and the glass substrate layer. The interposer may be used for forming an integrated circuit package. The integrated circuit package includes multiple integrated circuits that are mounted on the interposer.


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