IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9425057 B1

PDFFull Text
Date of Patent:
Aug. 23, 2016

Filed:

Oct. 06, 2011

Method and apparatus for manufacturing three-dimensional-structure memory device

Applicants:

Sung Kil Cho, Gyeonggi-do, KR;

Hai Won Kim, Gyeonggi-do, KR;

Sang Ho Woo, Gyeonggi-do, KR;

Seung Woo Shin, Gyeonggi-do, KR;

Gil Sun Jang, Chungcheongnam-do, KR;

Wan Suk OH, Gyeonggi-do, KR;

Inventors:

Sung Kil Cho, Gyeonggi-do, KR;

Hai Won Kim, Gyeonggi-do, KR;

Sang Ho Woo, Gyeonggi-do, KR;

Seung Woo Shin, Gyeonggi-do, KR;

Gil Sun Jang, Chungcheongnam-do, KR;

Wan Suk Oh, Gyeonggi-do, KR;

Assignee:

Eugene Technology Co., Ltd., Yonging-si, Gyeonggi-do, KR;

Attorney:

Rabin & Berdo, P.C.

Primary Examiner:

Nadine Norton

Assistant Examiner:

Erin Bergner

Int. Cl.
CPC ...
H01L 21/306 (2006.01); C23C 16/458 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30604 (2013.01); C23C 16/4585 (2013.01); H01L 21/02126 (2013.01); H01L 21/02129 (2013.01); H01L 21/02164 (2013.01); H01L 21/02211 (2013.01); H01L 21/02271 (2013.01); H01L 21/31111 (2013.01); H01L 21/67069 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01);
Abstract

A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH, SiH, SiH, SiH, and the step for laminating the sacrificial layer includes a step for depositing a second silicon oxide film by supplying dichlorosilane (SiClH) to the substrate.

Find Patent Forward Citations

Loading…