The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Jul. 17, 2014
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Kikuko Sugimae, Yokohama, JP;

Reika Ichihara, Yokohama, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0002 (2013.01); G11C 13/0011 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01); G11C 2213/71 (2013.01); G11C 2213/73 (2013.01);
Abstract

A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit repeating: applying a first voltage for setting to the memory cell; and a verify read verifying that the resistance value of the memory cell has become lower than the predetermined resistance value. After the verify read, the control circuit applies a second voltage having a different polarity from the first voltage to the memory cell before applying the first voltage that follows.


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