The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Jun. 22, 2012
Applicants:

Cas Groot, Antwerp, BE;

Maurits Storms, Best, NL;

Inventors:

Cas Groot, Antwerp, BE;

Maurits Storms, Best, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G11C 7/20 (2006.01); G11C 16/20 (2006.01); G06F 3/06 (2006.01); G06F 15/177 (2006.01); G06F 1/32 (2006.01); G06F 11/14 (2006.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G11C 7/20 (2013.01); G11C 16/20 (2013.01); G06F 1/3275 (2013.01); G06F 3/065 (2013.01); G06F 3/0632 (2013.01); G06F 11/1402 (2013.01); G06F 12/0646 (2013.01); G06F 15/177 (2013.01);
Abstract

Embodiments of a method for operating a computer system are disclosed. In one embodiment, the memory unit has a non-volatile memory array and processing logic and the non-volatile memory array stores initialization data that is used by the processing logic to perform input/output operations of the memory unit. The method involves storing the initialization data in retention registers within the memory unit, wherein the retention registers are separate from the non-volatile memory array and retain data while the memory unit is power gated, using the stored initialization data in the retention registers to initialize the memory unit upon exiting the power gating.


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