The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2016
Filed:
Sep. 17, 2013
Boe Technology Group Co., Ltd., Beijing, CN;
Hefei Boe Optoelectronics Technology Co., Ltd., Hefei, Anhui, CN;
Ming Li, Beijing, CN;
Jongseok Jang, Beijing, CN;
Yong Sub Kim, Beijing, CN;
Xiaotao Liu, Beijing, CN;
BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;
HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Hefei, Anhui, CN;
Abstract
A test method for line defect in a display panel () comprises: inputting a first ON signal and a first OFF signal into odd rows of gate scanning lines (GE) and even rows of gate scanning lines (GS) of the display panel () respectively, to turn on transistors controlled by the odd rows of gate scanning lines (GE), and turn off transistors controlled by the even rows of gate scanning lines (GS), thereby obtaining a first test image; inputting a second OFF signal and a second ON signal into the odd rows of gate scanning lines (GE) and even rows of gate scanning lines (GS) of the display panel () respectively, to turn off the transistors controlled by the odd rows of gate scanning lines (GE), and turn on the transistors controlled by the even rows of gate scanning lines (GE), thereby obtaining a second test image; comparing the first test image with the second test image to determine that line display defect appearing in the first test image or the second test image are true display defect. Also is disclosed a test device for line defect in a display panel (). This method allows the test result to approach the lighting test result under module signal input state and can detect true defect of the display panel ().
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile