The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Oct. 10, 2014
Applicant:

Mie Fujitsu Semiconductor Limited, Kuwana, JP;

Inventors:

George Tien, Cupertino, CA (US);

David A. Kidd, San Jose, CA (US);

Lawrence T. Clark, Phoenix, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5068 (2013.01); G06F 17/5081 (2013.01); G06F 2217/02 (2013.01); G06F 2217/06 (2013.01); G06F 2217/12 (2013.01); H01L 27/0207 (2013.01);
Abstract

A method for modifying a design of an integrated circuit includes obtaining design layout data for the integrated circuit and selecting at least one SRAM cell in the integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer. The method also includes extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout. The method further includes adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the SRAM cell and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.


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