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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9424178 B1

PDFFull Text
Date of Patent:
Aug. 23, 2016

Filed:

Jun. 21, 2011

Optimized flash memory without dedicated parity area and with reduced array size

Applicants:

Eran Sharon, Rishon Lezion, IL;

Idan Alrod, Herzliya, IL;

Simon Litsyn, Giv'at Shmuel, IL;

Inventors:

Eran Sharon, Rishon Lezion, IL;

Idan Alrod, Herzliya, IL;

Simon Litsyn, Giv'at Shmuel, IL;

Assignee:

Sandisk IL Ltd., Kfar Saba, IL;

Attorney:

Alston & Bird LLP

Primary Examiner:

Charles Rones

Assistant Examiner:

Tian-Pong Chang

Int. Cl.
CPC ...
G06F 12/02 (2006.01); H03M 13/05 (2006.01); G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 7/10 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 11/1072 (2013.01); G06F 11/1076 (2013.01); G11C 11/5628 (2013.01); G11C 16/10 (2013.01); H03M 13/05 (2013.01); G11C 7/1006 (2013.01); G11C 29/00 (2013.01); G11C 2211/5641 (2013.01);
Abstract

A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.

Find Patent Forward Citations

Sharon, Eran. (2016). Optimized flash memory without dedicated parity area and with reduced array size (U.S. Patent No. 9424178). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9424178

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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