The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Jul. 08, 2013
Applicants:

Stmicroelectronics (Beijing) R&d Company Ltd., Beijing, CN;

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

PengFei Zhu, Bejing, CN;

HongXia Sun, Bejing, CN;

YongQiang Wu, Bejing, CN;

Elio Guidetti, Montano Lucino, IT;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/76 (2006.01); G06F 13/00 (2006.01); G06F 9/30 (2006.01); G06F 9/345 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3004 (2013.01); G06F 9/30043 (2013.01); G06F 9/30112 (2013.01); G06F 9/30127 (2013.01); G06F 9/345 (2013.01); G06F 9/3824 (2013.01); G06F 9/3893 (2013.01);
Abstract

Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.


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