The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Jul. 31, 2014
Applicant:

Fairchild Semiconductor Corporation, San Jose, CA (US);

Inventor:

Robert A. Card, Scarborough, ME (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/81 (2013.01); G06F 1/04 (2006.01); G06F 21/62 (2013.01); G06F 21/85 (2013.01); G09C 1/00 (2006.01); H04L 9/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/04 (2013.01); G06F 21/629 (2013.01); G06F 21/85 (2013.01); G09C 1/00 (2013.01); H04L 9/003 (2013.01); H04L 2209/04 (2013.01); H04L 2209/08 (2013.01); Y04S 40/24 (2013.01);
Abstract

This document discusses, among other things, systems and methods to communicate data over a data bus during a first period of a clock signal with a uniform power distribution, including providing a complimentary bit state of the data during a first portion of the first period of the clock signal and providing an actual bit state of the data during a second portion of the first period of the clock signal. In an example, the first period can include first, second, third, and fourth portions, and the systems and methods can include providing a complimentary bit state of the data during first and fourth portions of the first period of the clock signal and an actual bit state of the data during a second portion of the first period of the clock signal.


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