The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Mar. 27, 2015
Applicant:

Mstar Semiconductor, Inc., Hsinchu Hsein, TW;

Inventors:

Po-Nien Lin, Zhubei, TW;

Meng-Tse Weng, Zhubei, TW;

Jiunn-Yih Lee, Zhubei, TW;

Assignee:

MStar Semiconductor, Inc., Hsinchu Hsien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H03L 7/08 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
H04L 7/033 (2013.01); H03L 7/081 (2013.01); H03L 7/0807 (2013.01); H04L 7/0337 (2013.01);
Abstract

A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.


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