The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2016
Filed:
Aug. 07, 2014
Applicant:
SK Hynix Memory Solutions Inc., San Jose, CA (US);
Inventors:
Assignee:
SK Hynix memory solutions Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); H04L 1/00 (2006.01); G06F 11/10 (2006.01); H03M 13/11 (2006.01); H03M 13/29 (2006.01); H03M 13/37 (2006.01); H03M 13/00 (2006.01); H03M 13/41 (2006.01);
U.S. Cl.
CPC ...
H04L 1/004 (2013.01); G06F 11/10 (2013.01); H03M 13/1111 (2013.01); H03M 13/2933 (2013.01); H03M 13/3715 (2013.01); H03M 13/3738 (2013.01); H03M 13/6502 (2013.01); H03M 13/6508 (2013.01); H04L 1/005 (2013.01); H04L 1/0053 (2013.01); H03M 13/4138 (2013.01);
Abstract
A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.