The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Dec. 29, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Sreenath Narayanan Potty, Trivandrum, IN (US);

Vivek Singhal, Karnataka, IN;

Sumanth Reddy Poddutur, Karnataka, IN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); H03K 3/00 (2006.01); H03L 7/081 (2006.01); H03K 3/013 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0818 (2013.01); H03K 3/013 (2013.01);
Abstract

A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.


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