The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2016
Filed:
Mar. 01, 2016
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Assignee:
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/081 (2006.01); H03L 7/091 (2006.01); H03L 7/089 (2006.01); H03L 7/093 (2006.01); H03K 5/14 (2014.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0812 (2013.01); H03K 5/14 (2013.01); H03L 7/0891 (2013.01); H03L 7/091 (2013.01); H03L 7/093 (2013.01); H03K 2005/00019 (2013.01);
Abstract
A delay-locked loop (DLL) has a fractional phase frequency (PF) detector that reduces false locking and harmonic locking. The PF detector has a trunk, an upper branch, a lower branch, and a logic module. A delay line provides the PF detector a set of fractional phase-delayed clock signals that are used to prime and/or activate corresponding flip-flops of the trunk, upper branch, and lower branch in a sequence. The use of flip-flops in the lower branch activated by different fractional phase-delayed clock signals avoids false locking and harmonic locking over a wider range of initial delay magnitudes than conventional DLLs.