The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Sep. 18, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Venkateswara Reddy P, Bangalore, IN;

Vinayak Ghatawade, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0013 (2013.01); H03K 19/00361 (2013.01); H03K 19/018521 (2013.01); H03K 19/018592 (2013.01);
Abstract

An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode.


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