Semiconductor integrated circuit, apparatus including semiconductor integrated circuit, and method for controlling clock signal in semiconductor integrated circuit

Abstract

A semiconductor integrated circuit includes a first generation unit configured to generate a fixed frequency division clock signal (first signal) from an output clock signal of a clock source, a fixed frequency division state monitoring unit configured to monitor the first signal, a second generation unit configured to generate a variable frequency division clock signal (second signal) from the output signal, and a variable frequency division state monitoring unit configured to monitor the second signal. In a case where the frequency of the second signal is returned from a reduced frequency to normal, when the variable frequency division state monitoring unit determines that the second signal becomes high in a next cycle, output of the second signal is stopped, and when the fixed frequency division state monitoring unit determines, after the output is stopped, that the first signal becomes high in a next cycle, the output is resumed.