The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9419592 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 16, 2016

Filed:

Sep. 05, 2014
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Vibhu Sharma, Eindhoven, NL;

Jose de Jesus Pineda De Gyvez, Eindhoven, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); H03K 3/0375 (2013.01); H03K 3/356121 (2013.01); H03K 3/356139 (2013.01); H03K 3/356156 (2013.01);
Abstract

A sequential circuit arrangement and method are provided in which a latch input signal and a latched version of the input signal are compared to derive a difference signal. This difference signal can detect when changes in the input are not propagated to the output. A second logic gate arrangement derives an error signal from the product of difference signal and a delayed version of the difference signal. This means that normal operation of the circuit is not detected as an error—only when the latched output fails to follow the input after the normally expected delay is the error signal created. The latch element output or an inverted version of the latch element output is selected in dependence on the error signal.


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