Precision, high voltage, low power differential input stage with static and dynamic gate protection

Abstract

A precision, high voltage, low power differential input stage including static and dynamic gate protection is disclosed herein. The differential input stage incorporates the performance of low voltage transistors with the high voltage capability of high voltage transistors. The transistors may be MOSFETs or the like. In addition, gate protection is provided to protect against large DC voltages and AC voltage transitions. The differential input stage includes a pair of input circuits, such as positive and negative input circuits, each including a cascode combination of low and high voltage transistors. In each cascode stage, the low voltage transistor is fabricated with a gate threshold voltage that is as high or higher than that of the high voltage transistors. The low voltage, high threshold transistors in the cascode stages may be configured to match each other. Resistors and capacitors may be provided to protect against excessive input current and voltage.