The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2016
Filed:
May. 23, 2014
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Victor Korol, San Diego, CA (US);
Shu-Hsien Liao, San Diego, CA (US);
Assignee:
Qualcomm Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); H03F 1/02 (2006.01); H03F 3/193 (2006.01); H03F 3/21 (2006.01); H03F 1/22 (2006.01); H03F 1/52 (2006.01); H03F 3/24 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0205 (2013.01); H03F 1/0211 (2013.01); H03F 1/0261 (2013.01); H03F 1/0272 (2013.01); H03F 1/223 (2013.01); H03F 1/523 (2013.01); H03F 3/193 (2013.01); H03F 3/21 (2013.01); H03F 3/245 (2013.01); H03F 2200/18 (2013.01); H03F 2200/27 (2013.01); H03F 2200/451 (2013.01); H03F 2200/513 (2013.01); H03F 2200/61 (2013.01);
Abstract
An apparatus includes a plurality of stacked transistors in a multi-stacked power amplifier. At least one transistor of the plurality of stacked transistors is configured to operate in a first mode and in a second mode. The at least one transistor of the plurality of stacked transistors is configured to be biased by a low power biasing network to operate in the first mode.