The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Aug. 17, 2012
Applicants:

Qingqing Liang, Lagrangeville, NY (US);

Huicai Zhong, San Jose, CA (US);

Huilong Zhu, Poughkeepsie, NY (US);

Chao Zhao, Kessel-Io, BE;

Tianchun YE, Beijing, CN;

Inventors:

Qingqing Liang, Lagrangeville, NY (US);

Huicai Zhong, San Jose, CA (US);

Huilong Zhu, Poughkeepsie, NY (US);

Chao Zhao, Kessel-Io, BE;

Tianchun Ye, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7855 (2013.01);
Abstract

One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.


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