The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Nov. 20, 2012
Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

Seong Bo Shim, Kyoung-gi-Do, KR;

Kyung Oe Kim, Kyoung-gi-Do, KR;

Yong Hee Kang, Kyoung-gi-Do, KR;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/488 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H05K 3/34 (2006.01); H01L 21/50 (2006.01); H01L 23/482 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/48 (2013.01); H01L 21/4846 (2013.01); H01L 21/50 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H05K 3/3452 (2013.01); H01L 23/4824 (2013.01); H01L 24/04 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/48 (2013.01); H01L 24/81 (2013.01); H01L 25/105 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0558 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/131 (2013.01); H01L 2224/1308 (2013.01); H01L 2224/13016 (2013.01); H01L 2224/13019 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13099 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/274 (2013.01); H01L 2224/27013 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/8114 (2013.01); H01L 2224/8121 (2013.01); H01L 2224/81385 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/00013 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01015 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01049 (2013.01); H01L 2924/01073 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19041 (2013.01); H05K 2201/10674 (2013.01); H05K 2201/2081 (2013.01); H05K 2203/0315 (2013.01);
Abstract

A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around bumps between the semiconductor die and substrate.


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