Nonvolatile memory device maintaining a bitline precharge during program verification periods for multi-level memory cells and related programming method

Abstract

A nonvolatile memory device comprises a memory cell array comprising multiple memory cells disposed at intersections of corresponding word lines and bitlines, and multiple page buffers connected to the bitlines, respectively, and performing consecutive verify read operations on selected memory cells programmed in first to N-th logic states (N>2), wherein, in the consecutive verify read operations, the bitlines are placed in a precharged state by precharging them to a first level during a verification period of memory cells programmed in the first logic state, are maintained in the precharged state during verification periods of memory cells programmed in the second to (N−1)-th logic states, and are discharged after a verification period of memory cells programmed in the N-th logic state.