The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Feb. 08, 2012
Applicant:

Ted a Hadley, Sunnyvale, CA (US);

Inventor:

Ted A Hadley, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); H04L 9/32 (2006.01); G06F 21/54 (2013.01); G06F 21/75 (2013.01); H04L 9/08 (2006.01); G06F 1/24 (2006.01); G06F 21/57 (2013.01); G06F 12/14 (2006.01); G06F 21/60 (2013.01); G06F 21/55 (2013.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01); G06F 21/78 (2013.01); G09C 1/00 (2006.01); G06F 11/22 (2006.01); G06F 21/74 (2013.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1642 (2013.01); G06F 1/24 (2013.01); G06F 11/2284 (2013.01); G06F 12/1433 (2013.01); G06F 12/1483 (2013.01); G06F 13/1663 (2013.01); G06F 21/54 (2013.01); G06F 21/55 (2013.01); G06F 21/57 (2013.01); G06F 21/575 (2013.01); G06F 21/602 (2013.01); G06F 21/72 (2013.01); G06F 21/74 (2013.01); G06F 21/75 (2013.01); G06F 21/78 (2013.01); G06F 21/79 (2013.01); G09C 1/00 (2013.01); H04L 9/088 (2013.01); H04L 9/0816 (2013.01); H04L 9/32 (2013.01); G01R 31/31719 (2013.01); G06F 2221/2143 (2013.01); H04L 2209/12 (2013.01);
Abstract

In one implementation, a processor is provided that includes logic to enable a transition from a zeroize state to a clear state. In another implementation, a processor is provided that includes logic to enable a testing secure state, the testing state to enable a testing function; logic to enable a clear state, the clear state to enable a non-secure processing function and to disable a security function; logic to enable a transition from a testing secure state to a clear state; and logic to enable a full secure state, the full secure state to enable the processing function. In another implementation, a processor is provided that includes logic to disable a transition from a clear state to a secure state.


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