The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Mar. 19, 2015
Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Jean-Marc Daveau, Grenoble, FR;

Sylvain Clerc, Grenoble, FR;

Philippe Roche, Biviers, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/08 (2006.01); G01R 31/3177 (2006.01); G06F 11/267 (2006.01); G01R 31/3185 (2006.01); G06F 11/18 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G06F 11/267 (2013.01); G01R 31/318502 (2013.01); G06F 11/183 (2013.01);
Abstract

A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.


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