The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2016

Filed:

Dec. 14, 2012
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventors:

Hayato Nakamura, Kyoto, JP;

Eigo Tange, Kyoto, JP;

Tadashi Matsuoka, Kyoto, JP;

Yasushi Shigeno, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 1/44 (2006.01); H04W 88/02 (2009.01); H04B 1/00 (2006.01);
U.S. Cl.
CPC ...
H04B 1/44 (2013.01); H04B 1/006 (2013.01); H04B 1/0064 (2013.01); H04B 1/0067 (2013.01); H04W 88/02 (2013.01);
Abstract

Provided is a high frequency module capable of reducing the IMD. During the transmission/reception operation based on W-CDMA, control signals VSWCC, VTRXCC are output as Hi signals from a control logic. Consequently, transistor Tis turned ON, and transistors T, Tare respectively turned OFF. When the transistor Tis turned ON, the voltage output from an operational amplifier is output as the signal VVSW to a control terminal, and the control signal VTRXC is output as a Hi signal. The signal VVSW is of a voltage level that is lower than that of the control signal VTRXC. The control signal VTRXC is a signal for turning ON a transistor circuit Q, and the signal VVSW is a signal for supplying a DC voltage to the antenna potential. It is thereby possible to reduce the ON resistance of the transistor circuit Qand improve the IMD characteristics.


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