Chip or soc including fusible logic array and functions to protect logic against reverse engineering

Abstract

A security chip including a fusible logic array. An input is configured to receive, from a verification module external to the security chip, a seed value corresponding to one of a predetermined value and a generated value. The fusible logic array is configured to generate a logic result using the received seed value. The fusible logic array includes a logic gate configured to operate, based on a state of a fusible link within the logic gate, as both a first type of logic gate configured to perform a first logic operation and a second type of logic gate configured to perform a second logic operation different from the first logic operation. The fusible logic array is configured to generate the logic result based on the state of the fusible link. An output is configured to provide a key value, representative of the logic result, to the verification module.