The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2016

Filed:

Jun. 12, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Jinchao Bai, Beijing, CN;

Zongjie Guo, Beijing, CN;

Xiangqian Ding, Beijing, CN;

Xiaowei Liu, Beijing, CN;

Yao Liu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1368 (2006.01); G02F 1/1362 (2006.01); H01L 29/49 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1218 (2013.01); G02F 1/1368 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1262 (2013.01); H01L 27/1288 (2013.01); H01L 29/45 (2013.01); H01L 29/495 (2013.01); H01L 29/4908 (2013.01);
Abstract

An array substrate including a base substrate is disclosed; the base substrate is divided into a pixel region and a peripheral circuit region, the pixel region sequentially includes a gate electrode, a gate insulation layer, a semiconductor active layer, a pixel electrode, a source/drain electrode, a passivation layer and a common electrode; the peripheral circuit region sequentially includes a first circuit line, the gate insulation layer, a second circuit line and the passivation layer. An orthogonal projection area of the second circuit line is at least partly overlapped with an orthogonal projection area of the first circuit line on the base substrate, and the second circuit line is directly electrically connected with the first circuit line through a via hole penetrating the gate insulation layer. A method for manufacturing the array substrate and a display device including the array substrate are also disclosed.


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